Generally, as a method for compressing data of several bits into one bit data can inspect error of data of several bits using data of one bit physically, the inspection time and bit number can be reduced. Thus, this method is spotlighted as a method of testing a DRAM. A data compression method is mainly employed to inspect data of multiple bits using a data line of one bit.
Referring now to FIG. 1, a conventional circuit for inspecting a data error is described. A clock buffer 1 transfer a clock signal CLK inputted from the outside to a latch unit 3. A buffer unit 2 transfers a row address select signal/RAS, a column address select signal/CAS, a write enable signal /WE, a chip select signal/CS, a clock enable signal CKE and address signals AN<0:m>, all of which are inputted from the outside, to a DRAM. Based on the clock signal iclk outputted from the clock buffer 1, the latch unit 3 synchronizes an output signal of the buffer unit 2 for receiving the signals /RAS, /CAS, /WE, /CS, CKE and AN<0:m>. At this time, the clock signal iclk is a signal that becomes a HIGH level when the clock signal CLK becomes a HIGH level. The clock signal iclk may become a LOW level when the clock signal CLK becomes a LOW level or a LOW level because of a certain delay within the DRAM.
Each of the signals irasb, icasb, iweb and icsb outputted from the latch unit 3 becomes a HIGH level when the signals /RAS, /CAS, /WE and /CS become LOW levels. Each of the signals Ai<0:m> becomes a LOW level when the signals AN<0:m> become LOW levels.
FIG. 2 is a circuit diagram of the decoder 4 shown in FIG. 1. The inverter I1 inverts a signal icasb from the latch unit 3 to output an inverted signal icas.
The signals irasb, icasb, iweb and icsb from the latch unit 3 are inputted into a NAND gate G1. A NAND gate G2 may receive the output signal of the NAND gate G1, which is inverted by the inverter I2, and the address signal Ai<10> to output a reset signal reset.
The address signals Ai<0>, Ai<1>, Ai<2> and Ai<3> from the latch unit 3 are inputted to a NAND gate G3. The signals irasb, icasb, iweb and icsb from the latch unit 3 are inputted to a NAND gate G5. Also, an inverted signal of the NAND gate G5, which is inverted by the inverter I4, and an address signal Ai<7> are inputted to a NAND gate G6. Further, an output signal of the inverter 13 and an output signal of the NAND gate G6, which is inverted by the inverters I5, I6 and I7, are inputted into a NAND gate G4. A signal outputted from the NAND gate G4 is outputted to an output terminal tcomp through a latch circuit having NAND gates G7 and G8.
The decoder 4 described above operates so that an output signal tcomp of the decoder 4 becomes a HIGH level when the signals irasb, icasb, iweb, icsb, Ai<7>, Ai<0>, Ai<1>, Ai<2>, Ai<3>, or the like from the latch unit 3 are HIGH levels. The output signal tcomp becomes a LOW level when the signals irasb, iweb, icsb, Ai<10>, and the like are HIGH levels and the signal icasb is a LOW level. The decoder 4 operates in a data compression mode when the output signal tcomp is a HIGH level.
Although, a signal that is decoded to control the output signal tcomp is shown in FIG. 2, persons of ordinary skill in the art will readily appreciate that a decoding of another mode is possible.
FIG. 3 is a detailed circuit diagram of the compression unit 6 shown in FIG. 1. The signals gio<0> to gio<n> transferred through a data bus are inputted to a NAND gate G9 and the NOR gate G10. An output signal of the NAND gate G9 through the inverters I8 and I9, an output signal of the NOR gate G10 through the inverter I10, and the output signal tcomp of the decoder 4 are inputted to the NAND gate G11. A signal rdbc is outputted from the NAND gate G11.
The output signal rdbc becomes a HIGH level when the output signal tcomp of the decoder 4 is a HIGH level, and the signals gio<0:n> transferred through the data bus within the DRAM are HIGH levels or LOW levels. For all the case except for the above, the output signal rdbc becomes a LOW level (e.g., the output signal tcomp of the decoder 4 is a LOW level).
FIG. 4 is a detailed circuit diagram of the select unit 5 shown in FIG. 1. A signal gio<k> and a compressed signal rdbc are transferred to the data line rdb through the transmission means T1 and T2 that are driven by the output signal tcomp of the decoder 4 and an inverted signal tcompb.
When the output signal tcomp of the decoder 4 is a HIGH level, the signal rdbc outputted from the compression unit 6 is transferred to the one bit data line rdb. When the output signal tcomp of the decoder 4 is a LOW level, one signal gio<k> of the signals gio<0:n> transferred through the data bus is transferred to the data line rdb. As a result, in the data compression test mode, the signals gio<o:n> transferred through the data bus are compressed to become the signal rdbc, which in turn, is transferred to the data line rdb. For all other modes, the signal gio<k> is transferred to the data line rdb.
As noted above, when the signal rdbc compressed through the compression unit 6 does not contain information on the signals gio<0:n> and when the signal rdbc is a LOW level, it is difficult to determine which signal of the data bus signals gio<0:n> is a HIGH level and which is a LOW level using only the signal rdbc. In other words, in an error inspection test situation in which only the signal rdb being one bit data is outputted from the DRAM, it is difficult to determine which signal of the data bus signals gio<0:n> has an error. To inspect which signal of the data bus signals gio<0:n> has an error, there is an error inspecting environment by which the signals rdb of n bit corresponding to the signals gio<0:n>, respectively, are output from the DRAM to inspect an error.
The conventional error inspecting circuit does not contain data information of respective bits in data transferred through the data line of one bit. Accordingly, if an error of data occurs, it is difficult to determine which data has an error. As a result, in a test environment of DRAM using a conventional data compression method, there is a need for a test environment by which each of data of several bits can be inspected for error.